1. Field of the Invention
The present invention relates, in its more general aspect, to the field of the electronics with nanometric semiconductor electronic devices and to the field of the nano-manufacturing.
More in particular, the invention relates to a method for realizing a hosting structure of nanometric elements realized on a substrate by means of repeating deposition steps of layers of different materials alternating with anisotropic etching steps of these materials.
2. Description of the Related Art
As it is well known, in the field of the microelectronics the need of realizing circuit configurations of more and more reduced dimensions is particularly felt.
In the last thirty years, the progress of the electronic technology has followed a trend governed by that which is known as “Moore Law”, an empirical law stating that the capacity of storing information in memory devices doubles each eighteen months approximately, whereas the calculation performance of the CPUs (Central Processing Units) improve of a factor each twenty-four months, as reported in the diagram of FIG. 1.
The Moore law is based on the capacity of reducing the geometries of the considered devices and it highlights how dimensions have passed from being equal to 2 μm for the nineteen eighties technologies, to being equal to 130 nm in 2001, to currently being equal to 90 nm.
However, the current technology is quickly reaching the physical limits of its possibilities; in particular, the currently used photolithography processes are subject to drastic dimensional limitations for values being lower than 100 nm.
Forward techniques have thus been developed, such as x-ray non-optic lithography, extreme ultra-violet lithography and electronic-beam lithography, which allow to realize circuit configurations with dimensions in the order of some tens of nanometers.
These techniques, however, require complex instruments characterized by excessively long times of lithographic etching and they thus tend to be too expensive for being applied to a mass industrial manufacturing.
As an alternative, sub-lithographic patterning techniques have been developed based on controlled (conformable) deposition and of selective removal of a functional material on a suitable layer for realizing nanometric elements.
These techniques have allowed the adjustment of methods for realizing semiconductor substrates suitable for obtaining different typologies of components, as for example indicated in the U.S. Pat. Nos. 6,570,220 and 6,063,688 both to Doyle et. al.
In particular, in these patents a deep submicrometric structure is described for components and, respectively, a method for realizing it. This method provides the realization, on a silicon substrate by means of lithography, first spacers of a first material, whereon, by means of controlled deposition, a layer of a second material is realized. Moreover the thickness of the layer of the second material is approximately half the width of the first spacers.
The selective removal of the second material, carried out by means of anisotropic etching, thus defines second spacers, each being adjacent to respective side portions of the first spacers, and each having width equal to the thickness of the layer of this second material.
With a successive selective chemical etching the first spacers are removed, leaving on the surface of the semiconductor substrate only the second spacers. The deposition of a layer of a third material, controlled in the thickness, followed by a selective removal step by anisotropic etching, defines third spacers.
These third spacers, each adjacent to respective side portions of the second spacers, have a width equal to the thickness of the layer of the third material. With a selective chemical etching the second spacers are removed leaving on the semiconductor surface solely the third spacers.
The operations of controlled depositions, of anisotropic etching and of selective etching are repeated more than once to provide spacers of reduced width of 100 Å or less, which are separated from one another by a distance of around 200 Å. By depositing, finally, a dielectric material in the region defined between two consecutive spacers, a conductive region is realized which can be used for realizing a CMOS transistor.
The above method needs, however, a preliminary and accurate programming since each realization step of an n order (with n≧2) of spacers is followed by a removal step of the spacers of the previous order (n−1), and it is thus necessary to provide a suitable distance and a suitable thickness of the first spacers for realizing last spacers of desired dimensions.
In the U.S. Pat. No. 6,187,694 to Cheng et al. a method is also described for realizing a structure of an integrated circuit, for example a gate electrode of a MOS transistor, by using two edge definition layers and a spacer realized above a substrate. The gate electrode is realized, on the substrate portion below the spacer, by means of a succession of chemical etchings, each suitable for selectively removing portions of edge definition layers and substrate portions. These selective etchings are preceded by depositions of materials by means of masking.
Finally, in U.S. Pat. No. 6,664,173 to Doyle et al., a technique is described for patterning a hard mask gate, for all the typologies of components, by using a gate spacer for approaching nanometric masks. This technique provides starting from a unit comprising a substrate whereon first gate and respectively hard mask layers and subsequent second gate and hard mask layers are deposited.
On the second hard mask layer, by means of deposition followed by etching steps, a nanometric spacer is defined and used as a mask for realizing a gate electrode for a first transistor.
From the first hard mask layer of the same unit a structure is realized for a second transistor after further deposition and etching steps.
Subsequent steps are however required for realizing a MOS device.
Although satisfying the aim, this method is limited in that it allows to realize, although of nanometric dimensions, a single gate electrode for a transistor.
In substance, all the known methods are inadequate to fulfill the need of realizing nanometric structures with suitable conduction and control terminals for use as semiconductor electronic devices.